Physical Design Engineer
Einfochips
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About this role
Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners. Partner with the design team to proactively identify and address potential physical design challenges, enablin…
Read the full description and requirements on the original posting.
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Einfochips and most employers screen applications with ATS software before a recruiter reads them, and they rank resumes that echo the language of the posting. To stand out for this role, mirror the exact skills, tools, and job title it uses, and make your location (San Jose, Santa Clara County) clear.
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Build a matching resume — freeFrequently asked questions
Is the Physical Design Engineer role at Einfochips remote?
This role is based in San Jose, Santa Clara County. Check the original posting for any hybrid or remote flexibility.
What does the Physical Design Engineer role at Einfochips pay?
The listed pay is 120k–140k. Salaries vary with experience and location — treat this as a guide and confirm on the original posting.
How do I apply for this Physical Design Engineer job?
Applications happen on the employer's own site — use the "Apply on company site" link on this page. Before you apply, tailor your resume to the listing so it clears the ATS.
How do I tailor my resume for this Physical Design Engineer role?
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Listing sourced via Adzuna. Tailr indexes public job postings so you can tailor your resume to them — applications happen on the employer's site.